This invention relates to a method and apparatus for defect detection in a semiconductor structure having a plurality of self-aligned contacts. More specifically, it relates to detection of defects caused by the self-aligned contact etch process.
Self-aligned contacts are typically utilized in densely packed array structures, such as a DRAM memory structure. FIG. 1A is a diagrammatic side view of a partially fabricated self-aligned contact 100 prior to the self-aligned contact etch process. Initially, a source or drain 104 is formed in a substrate 102 such as silicon. A gate oxide 106 is then deposited over the substrate 102 and source or drain 104. A gate 108 is then formed from a conductive material, such as polysilicon or tungsten silicide. Dielectric or insulating spacers 110 (e.g., SiO2) are then formed and patterned around the gate 108. A thin insulating layer 112 is then formed and patterned over the gate oxide 106, the spacers 110, and the source or drain 104. A dielectric layer 114 (e.g., SiO2, FSG, Low K) is then deposited over the gate oxide 106, the thin insulating layer 112, and the source or drain 104. The dielectric layer 114 is patterned for contact/via 122 and etched such that a contact is formed to the substrate 102 through the gate oxide 106.
The thin insulating layer 112 is typically formed from a material that serves as a barrier to the subsequent self-aligned contact etch process. For example, the barrier 112 is typically a nitride material (e.g., Si3N4 or SiON that is 30 to 40 nm thick), and the self-aligned contact etch is selected to not etch a nitride material. FIG. 1B illustrates a diagrammatic side view of the self-aligned contact after the self-aligned contact etch process completes without etching through the thin insulating layer 112. As shown, the self-aligned contact etch process typically etches through the dielectric material 114 but not the barrier material 112 to form a via 124. That is, the etching process selectively etches the dielectric material 114. Accordingly, the gate 108 remains electrically isolated from the via 124 as a result of the thin insulating layer 112. A conductive plug 116 is then deposited (e.g., by chemical or physical vapor deposition) into via 124. The conductive plug may be any suitable conductive material, such as tungsten. A conductive line 118 is then formed and patterned over the conductive plug 116a. When the self-aligned contact etch process is selective, the gate 108 remains electrically isolated from the source or drain 104, the conductive plug 116a, and the conductive line 118.
FIG. 1C is a diagrammatic side view of a self-aligned contact 100′ with a barrier layer 112′ that has been breached by the self-aligned contact etch process. The barrier layer 112′ may be breached when the etching process fails to be selective. As a result of this failure, the gate 108 is now electrically coupled with the source or drain 104, the electric plug 116′, and the conductive line 118. Of course, this defect 120 is a killer defect since the transistor is no longer capable of functioning properly.
Several techniques are available for detecting defects caused by the self-aligned contact etch process. However, these techniques are typically performed after the wafer is removed from the fabrication line and after formation of the conductive lines (e.g., 118) that tie the self-aligned contact structures together. In one technique, the wafer is probed off-line to determine whether the conductive lines are shorted to the gates. Large conductive pads are typically formed within this conductive layer to facilitate probing. Hence, this technique requires extra real estate in the form of probe pads for the probe testing.
Another technique employs “short loop” wafers that are specifically designed to test a particular type of structure, such as a self-aligned contact structure. Short loop wafers are formed with a subset of fabrication steps. The subset of fabrication steps include key steps for forming the structure to be tested. For example, a “gate short loop” is formed from a patterned oxide layer and a patterned polysilicon layer. After the short loop wafer is fabricated, the resulting structures (e.g., gate structures) may then be tested via probing. This technique is extremely inefficient since extra masks are necessarily designed for the short loop wafer. Additionally, special process flows are required for the short loop wafer, in addition to the process flows required for the product wafers.
Both techniques require that the particular structure be completely fabricated prior to testing. The probe technique waits for completion of the conductive lines, and the short loop technique waits for completion of the short loop wafer. Thus, the product remains at risk during these waits. That is, defects can only be detected after the structure is completely fabricated. If there is a problem in an initial process step, this problem is not caught until after several process steps are subsequently completed. Additionally, both techniques require off-line probing. A probe test is also typically performed on a chain of structures (e.g., self-aligned contact structures) and, hence, only indicates whether a defect is present (or how many defects are present within the chain) and does not indicate a defect's location.
Accordingly, there is a need for improved apparatus and methods for detecting in-line defects in self-aligned contact structures and/or determining defect locations.